video.h

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/*---------------------------------------------------------------------------------
 
    Video registers and defines
 
    Copyright (C) 2012-2017
        Alekmaul
 
    This software is provided 'as-is', without any express or implied
    warranty.  In no event will the authors be held liable for any
    damages arising from the use of this software.
 
    Permission is granted to anyone to use this software for any
    purpose, including commercial applications, and to alter it and
    redistribute it freely, subject to the following restrictions:
 
    1.  The origin of this software must not be misrepresented; you
        must not claim that you wrote the original software. If you use
        this software in a product, an acknowledgment in the product
        documentation would be appreciated but is not required.
    2.  Altered source versions must be plainly marked as such, and
        must not be misrepresented as being the original software.
    3.  This notice may not be removed or altered from any source
        distribution.
 
---------------------------------------------------------------------------------*/
 
#ifndef SNES_VIDEO_INCLUDE
#define SNES_VIDEO_INCLUDE
 
#include <snes/snestypes.h>
 
typedef enum
{
    DSP_FORCEVBL = BIT(7), 
    VRAM_INCLOW = (0 << 7), 
    VRAM_INCHIGH = (1 << 7),
    VRAM_ADRTR_0B = (0 << 2),     
    VRAM_ADRTR_8B = (1 << 2),     
    VRAM_ADRTR_9B = (2 << 2),     
    VRAM_ADRTR_10B = (3 << 2),    
    VRAM_ADRSTINC_1 = (0 << 0),   
    VRAM_ADRSTINC_32 = (1 << 0),  
    VRAM_ADRSTINC_128 = (2 << 0) 
} VideoControl;
 
#define FADE_IN 2
#define FADE_OUT 1
#define MOSAIC_IN 2
#define MOSAIC_OUT 1
#define MOSAIC_BG1 (1 << 0)
#define MOSAIC_BG2 (1 << 1)
#define MOSAIC_BG3 (1 << 2)
#define MOSAIC_BG4 (1 << 3)
 
#define CM_DIRCOLOR (1 << 0) 
#define CM_SUBBGOBJ_ENABLE (1 << 1)
#define CM_ALWAYS_ENABLE (0 << 4)
#define CM_MATWIN_ENABLE (1 << 4)
#define CM_NOMATWIN_ENABLE (2 << 4)
#define CM_NEVER_ENABLE (3 << 4)
#define CM_SCBLK_ALWAYS_ENABLE (0 << 6)
#define CM_SCBLK_MATWIN_ENABLE (1 << 6)
#define CM_SCBLK_NOMATWIN_ENABLE (2 << 6)
#define CM_SCBLK_NEVER_ENABLE (3 << 6)
 
#define CM_SUB_MAINSUB (1 << 7)
#define CM_DIV2_DIVIDE (1 << 6)
#define CM_MSCR_BACK (1 << 5)
#define CM_MSCR_PAL47 (1 << 4)
#define CM_MSCR_BG4 (1 << 3)
#define CM_MSCR_BG3 (1 << 2)
#define CM_MSCR_BG2 (1 << 1)
#define CM_MSCR_BG1 (1 << 0)
 
#define CM_APPLY_BLUE (1 << 7)
#define CM_APPLY_GREEN (1 << 6)
#define CM_APPLY_RED (1 << 5)
 
#define M7_HFLIP (1 << 0)    
#define M7_VFLIP (1 << 1)    
#define M7_WRAP (1 << 6)     
#define M7_OUTTRANS (2 << 6) 
#define M7_OUTTILE (3 << 6)  
#define PPU_50HZ (1 << 4) 
#define REG_INIDISP (*(vuint8 *)0x2100)
 
#define REG_VMAIN (*(vuint8 *)0x2115)
 
#define REG_VMADDLH (*(vuint16 *)0x2116)
 
/*
    Writing to 2118h or 2119h does simply modify the LSB or MSB of the currently addressed VRAM
    word (with optional Address Translation applied). Depending on the Increment Mode the address
    does (or doesn't) get automatically incremented after the write.
*/
#define REG_VMDATAL (*(vuint8 *)0x2118)   
#define REG_VMDATAH (*(vuint8 *)0x2119)   
#define REG_VMDATALH (*(vuint16 *)0x2118) 
#define REG_CGADD (*(vuint8 *)0x2121)
 
#define CGRAM_PALETTE ((u8 *)0x2122)
 
#define REG_CGWSEL (*(vuint8 *)0x2130)
 
#define REG_CGADSUB (*(vuint8 *)0x2131)
 
#define REG_COLDATA (*(vuint8 *)0x2132)
 
#define REG_M7SEL (*(vuint8 *)0x211A)
 
/* 1st Write: Lower 8bit  ;\1st/2nd write mechanism uses "M7_old"
  2nd Write: Upper 8bit  ;/
*/
#define REG_M7A (*(vuint8 *)0x211B)    
#define REG_M7B (*(vuint8 *)0x211C)    
#define REG_M7C (*(vuint8 *)0x211D)    
#define REG_M7D (*(vuint8 *)0x211E)    
#define REG_M7HOFS (*(vuint8 *)0x210D) 
#define REG_M7VOFS (*(vuint8 *)0x210E) 
#define REG_M7X (*(vuint8 *)0x211F)    
#define REG_M7Y (*(vuint8 *)0x2120)    
/* After writing to 211Bh or 211Ch, the result can be read immediately from 2134h-2136h (the 21xxh Ports
  are rapidly clocked by the PPU, there's no delay needed when reading via "MOV A,[211Ch]" or via
  "MOV A,[1Ch]" (with D=2100h), both works even when the CPU runs at 3.5MHz).
*/
#define REG_MPYL (*(vuint8 *)0x2134)   
#define REG_MPYM (*(vuint8 *)0x2135)   
#define REG_MPYH (*(vuint8 *)0x2136)   
#define REG_MPYMH (*(vuint16 *)0x2135) 
#define REG_STAT77 (*(vuint8 *)0x213E)
 
#define REG_STAT78 (*(vuint8 *)0x213F)
 
// macro creates a 15 bit color from 3x5 bit components
#define RGB8(r, g, b) (((r) >> 3) | (((g) >> 3) << 5) | (((b) >> 3) << 10))
#define RGB5(r, g, b) ((r) | ((g) << 5) | ((b) << 10))
 
#define SCREEN_HEIGHT 224 
#define SCREEN_WIDTH 256  
extern u8 videoMode;    
extern u8 videoModeSub; 
extern u16 snes_frame_count; 
void setBrightness(u8 level);
 
void setMode(u8 mode, u8 size);
 
void setScreenOn(void);
 
void setScreenOff(void);
 
void setFadeEffect(u8 mode);
 
void setFadeEffectEx(u8 mode, u8 framesNumber);
 
void setMosaicEffect(u8 mode, u8 bgNumbers);
 
void setColorEffect(u8 colorMathA, u8 colorMathB);
 
void setColorIntensity(u8 colorApply, u8 intensity);
 
#define setPalette(palette, paletteEntry, paletteSize) dmaCopyCGram(palette, paletteEntry, paletteSize)
 
#define setPaletteColor(paletteEntry, paletteColor) \
    REG_CGADD = paletteEntry;                       \
    *CGRAM_PALETTE = (paletteColor)&0xFF;           \
    *CGRAM_PALETTE = (paletteColor) >> 8;
 
void getPalette(u8 paletteEntry, u8 paletteSize, u16 *paletteColors);
 
void getPaletteColor(u8 paletteEntry, u16 *paletteColor);
 
void setMode7(u8 mode);
 
void setMode7Rot(u8 angle);
 
void setMode7MoveForwardBack(u8 z8);
 
void setMode7MoveLeftRight(u8 z8);
 
void setMode7Angle(u8 angle);
 
void setMode7Scale(u16 xscale, u16 yscale);
 
unsigned short getFPScounter(void);
 
void showFPScounter(void);
 
#endif // SNES_VIDEO_INCLUDE