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#define | DMA_ENABLE 1 |
| Bit defines for the DMA control registers.
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#define | HDMA_CHANNEL0 (1 << 0) |
| Bit defines for the HDMA channels.
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#define | MSWIN1_BG1MSKENABLE (2 << 0) |
| Window 1 area BG1 enable.
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#define | MSWIN1_BG1MSKOUT (1 << 0) |
| Window 1 area BG1 inside (0) outside(1)
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#define | MSWIN1_BG2MSKENABLE (2 << 4) |
| Window 1 area BG2 enable.
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#define | MSWIN1_BG2MSKOUT (1 << 4) |
| Window 1 area BG2 inside (0) outside(1)
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#define | MSWIN1_BG3MSKENABLE (2 << 0) |
| Window 1 area BG3 enable.
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#define | MSWIN1_BG3MSKOUT (1 << 0) |
| Window 1 area BG3 inside (0) outside(1)
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#define | MSWIN1_BG4MSKENABLE (2 << 4) |
| Window 1 area BG4 enable.
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#define | MSWIN1_BG4MSKOUT (1 << 4) |
| Window 1 area BG4 inside (0) outside(1)
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#define | MSWIN2_BG1MSKENABLE (2 << 2) |
| Window 2 area BG1 enable.
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#define | MSWIN2_BG1MSKOUT (1 << 2) |
| Window 2 area BG1 inside (0) outside(1)
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#define | MSWIN2_BG2MSKENABLE (2 << 4) |
| Window 2 area BG2 enable.
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#define | MSWIN2_BG2MSKOUT (1 << 4) |
| Window 2 area BG2 inside (0) outside(1)
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#define | MSWIN2_BG3MSKENABLE (2 << 2) |
| Window 2 area BG3 enable.
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#define | MSWIN2_BG3MSKOUT (1 << 2) |
| Window 2 area BG3 inside (0) outside(1)
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#define | MSWIN2_BG4MSKENABLE (2 << 4) |
| Window 2 area BG4 enable.
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#define | MSWIN2_BG4MSKOUT (1 << 4) |
| Window 2 area BG4 inside (0) outside(1)
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#define | MSWIN_BG1 (1 << 0) |
| Bit defines for the window area main screen effect. More...
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#define | MSWIN_BG2 (1 << 1) |
| Main Screen BG2 disable background.
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#define | MSWIN_BG3 (1 << 2) |
| Main Screen BG3 disable background.
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#define | MSWIN_BG4 (1 << 3) |
| Main Screen BG4 disable background.
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#define | REG_A1B7 (*(vuint8 *)0x4374) |
| A1TxL - HDMA Table Start Address (low) / DMA Current Addr (low) (R/W) A1TxH - HDMA Table Start Address (hi) / DMA Current Addr (hi) (R/W) A1Bx - HDMA Table Start Address (bank) / DMA Current Addr (bank) (R/W) More...
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#define | REG_BBAD7 (*(vuint8 *)0x4371) |
| DMA/HDMA I/O-Bus Address (PPU-Bus aka B-Bus) (R/W) For both DMA and HDMA: 7-0 B-Bus Address (selects an I/O Port which is mapped to 2100h-21FFh)
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#define | REG_DAS7LH (*(vuint16 *)0x4375) |
| Indirect HDMA Address (low) / DMA Byte-Counter (low) (R/W) DASxL - Indirect HDMA Address (low) / DMA Byte-Counter (low) (R/W) DASxH - Indirect HDMA Address (hi) / DMA Byte-Counter (hi) (R/W) 43x7h - DASBx - Indirect HDMA Address (bank) (R/W) More...
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#define | REG_HDMAEN (*(vuint8 *)0x420C) |
| Select H-Blank DMA (H-DMA) Channel(s) (W) 7-0 H-DMA Channel 7-0 Enable (0=Disable, 1=Enable)
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#define | REG_MDMAEN (*(vuint8 *)0x420B) |
| Select General Purpose DMA Channel(s) and Start Transfer (W) 7-0 General Purpose DMA Channel 7-0 Enable (0=Disable, 1=Enable) More...
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void | dmaClearVram (void) |
| clear all vram data with #0
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void | dmaCopyCGram (u8 *source, u16 address, u16 size) |
| copy data from source to destination using channel 0 of DMA available channels in half words More...
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void | dmaCopyOAram (u8 *source, u16 address, u16 size) |
| copies Sprites from source to destination using channel 0 of DMA available channels in half words More...
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void | dmaCopySpr16Vram (u8 *source, u16 address) |
| copy sprite 16pix size data from source to destination using channel 0 of DMA available channels in half words More...
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void | dmaCopySpr32Vram (u8 *source, u16 address) |
| copy sprite 32pix size data from source to destination using channel 0 of DMA available channels in half words More...
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void | dmaCopyVram (u8 *source, u16 address, u16 size) |
| copy data from source to destination using channel 0 of DMA available channels in half words More...
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void | dmaCopyVram7 (u8 *source, u16 address, u16 size, u8 vrammodeinc, u16 dmacontrol) |
| copies data from source to destination using channel 0 of DMA available channels in half words with VMAIN value More...
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void | dmaFillVram (u8 *source, u16 address, u16 size) |
| fill the source data to destination using channel 0 of DMA available channels in half words More...
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void | setModeHdmaColor (u8 *hdmatable) |
| Do a color gradient effect on screen (with color 0). Use HDMA Channels 6. More...
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void | setModeHdmaGradient (u8 maxLevels) |
| Do a brightness gradient on screen. Use HDMA Channels 3. More...
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void | setModeHdmaReset (u8 channels) |
| Reset or Set HDMA channels. More...
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void | setModeHdmaShadeUpDown (void) |
| Do a brightness gradient from up/down to center of the screen. Use HDMA Channels 3.
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void | setModeHdmaShading (unsigned char mode) |
| Do a shading effect on screen. Use HDMA Channels 0 to 2. More...
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void | setModeHdmaWaves (u8 bgrnd) |
| Do a waves effect on screen (init function). Use HDMA Channels 6. More...
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void | setModeHdmaWavesMove (void) |
| Animate the waves effect. Must be called during each frame.
setModeHdmaWaves must have been done to init it.
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void | setModeHdmaWindowReset (u8 channels) |
| Reset or Set HDMA channels and remove WINDOW effect. More...
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void | setParallaxScrolling (u8 bgrnd) |
| Do a parallax scrolling effect on screen. Use HDMA Channels 3. More...
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Wrapper functions for direct memory access hardware.
#define REG_A1B7 (*(vuint8 *)0x4374) |
A1TxL - HDMA Table Start Address (low) / DMA Current Addr (low) (R/W) A1TxH - HDMA Table Start Address (hi) / DMA Current Addr (hi) (R/W) A1Bx - HDMA Table Start Address (bank) / DMA Current Addr (bank) (R/W)
For normal DMA: 23-16 CPU-Bus Data Address Bank (constant, not incremented/decremented) 15-0 CPU-Bus Data Address (incremented/decremented/fixed, as selected)
For HDMA: 23-16 CPU-Bus Table Address Bank (constant, bank number for 43x8h/43x9h) 15-0 CPU-Bus Table Address (constant, reload value for 43x8h/43x9h)
#define REG_DAS7LH (*(vuint16 *)0x4375) |
Indirect HDMA Address (low) / DMA Byte-Counter (low) (R/W) DASxL - Indirect HDMA Address (low) / DMA Byte-Counter (low) (R/W) DASxH - Indirect HDMA Address (hi) / DMA Byte-Counter (hi) (R/W) 43x7h - DASBx - Indirect HDMA Address (bank) (R/W)
For normal DMA: 23-16 Not used 15-0 Number of bytes to be transferred (1..FFFFh=1..FFFFh, or 0=10000h) (This is really a byte-counter; with a 4-byte "Transfer Unit", len=5 would transfer one whole Unit, plus the first byte of the second Unit.) (The 16bit value is decremented during transfer, and contains 0000h on end.)
#define REG_MDMAEN (*(vuint8 *)0x420B) |
Select General Purpose DMA Channel(s) and Start Transfer (W) 7-0 General Purpose DMA Channel 7-0 Enable (0=Disable, 1=Enable)
When writing a non-zero value to this register, general purpose DMA will be started immediately (after a few clk cycles). The CPU is paused during the transfer. The transfer can be interrupted by H-DMA transfers. If more than 1 bit is set in MDMAEN, then the separate transfers will be executed in WHICH? priority order. The MDMAEN bits are cleared automatically at transfer completion. Do not use channels for GP-DMA which are activated as H-DMA in HDMAEN.